CAS - RAS latency

Latency is the time it takes for the memory devices, after getting a command and address to produce its first data word. CAS latency is the clock cycles between the issuance of the read command and when the data comes out. This is a critical element of speed for PC100/133 memory. DIMMs with CAS latency 2 are faster than DIMMs with CAS latency 3. An 8ns DIMM with CAS latency 2 is faster than a 6ns DIMM with CAS latency 3. A 100 MHz DIMM operating at CAS latency 2 operates at 125 MHz enhancing system performance. A CAS 2 DIMM operates at 15-25% faster depending on system application. It is recommended that P-II & P-III and Athlon chips use CAS 2 DIMMS running at 100 or 133MHZ for extra speed, and crash free operation. What are RAS and CAS?      They stand for Row Access Strobe (RAS) and Column Access Strobe (CAS). Each describes how long it takes to read a row or column of memory cells, known as the CAS/RAS Latency. Each is described with a rating number, where lower numbers are better. The rating is also dependant on the front side bus speed of your motherboard so the rating may rise on higher speeds.      A common marketing term attached to SDRAM modules is either "CAS2" or "CAS3". Unfortunately, this is a bit misleading, as they should be referred to as CL2 or CL3, since they refer to CAS Latency timings (2 clocks vs. 3 clocks). As you have seen from the discussion above, the CAS Latency of a chip is determined by the column access time (tCAC). This is the time it takes to transfer the data to the output buffers from the time the /CAS line is activated.      The "rule" for determining CAS Latency timing is based on this equation: tCL = tCAC / tCLK      In lay terms, CAS Latency times the system clock cycle length must be greater than or equal to the column access time (tCAC). In other words, if tCLK is 10ns (100 MHz system clock) and tCAC is 20ns, the CAS Latency (CL) can be 2. But if tCAC is 25ns, then CAS Latency (CL) must be 3. The SDRAM specification permits CAS Latency values of 1, 2 or 3.

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Last Update: 10:36 PM 6/29/01