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BEDO DRAM (Burst Extended Data Output DRAM) |
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| Manufacturer: | many | Speed: | 25ns |
| Year Introduced: | 1995 | Frequency: | 40-66 MHz |
| Burst Timing: | 4-1-1-1 | Pins: | 72 |
| Voltage: | 5.0v | Bandwidth: | |
| Burst Extended Data Output DRAM (Burst EDO, BEDO) A variant on EDO DRAM in which read or write cycles are batched in bursts of four. The memory bursts wrap around on a four byte boundary which means that only the two least significant bits of the CAS (Column Address Strobe) are modified internally to produce each address of the burst sequence. Consequently, Burst EDO memory bus speeds will range from 40 MHz to 66 MHz , well above the 33 MHz bus speeds that can be accomplished using FPM (Fast Page Mode) or EDO DRAM. Burst EDO was available sometime before May 1995. BEDO DRAM can only stay synchronized with the Central Processing Unit clock for short periods (bursts). Also, it can not keep up with processors whose buses run faster than 66 MHz. Despite the fact that BEDO arguably provides more improvement over EDO than EDO does over FPM the standard has lacked chipset support and has consequently never really caught on, losing out to Synchronous DRAM (SDRAM). | |||